Frequency dividers are used in a large number of applications and may be implemented as circuits in which the input frequencies are integer multiples of the output frequencies. The maximum input frequency and the power consumption can typically be of concerns with regard to the frequency divider. Injection-locked frequency dividers (ILFDs) can be implemented to divide high frequencies, consuming generally less power than conventional frequency dividers (CML, dynamic logic, etc.), as they operate at the output rate as opposed to the input frequency.
Conventional frequency dividers are based on latches and registers. The digital approach allows easy implementation of almost any kind of division ratio, including odd division moduli (e.g. 3, 5, and so forth). For example, a divide-by-3 register-based divider consists of two positive edge-triggered registers (flip-flop) and an AND gate. The output is low for two cycles and high for one cycle of the input signal. Other frequency dividers, such as divide-by-5 dividers, divide-by-7 dividers, and so forth, can be implemented with similar architecture. For instance, in a divide-by-7 divider, the output would be low for four cycles and high for three cycles of the input signal.
Different implementations of registers may be used for a frequency divider having static or dynamic power consumption characteristics and a maximum achievable operation frequency. For example, the frequency divider may be implemented as a MOS current mode logic (MCML), true single phase clock logic (TSPC), enhanced true single phase clock logic (E-TSPC), and so forth. The disadvantage of conventional frequency dividers is the power consumption, which rises with the increase of input frequency.